1. Field of the Invention
The present invention relates to a semiconductor device, and relates, for example, to layouts of pads, power supply lines and buffer circuits in a semiconductor chip.
2. Description of the Related Art
Normally, a semiconductor chip is provided with pads for input/output of signals. In a conventionally widely adopted pad layout, pad arrays are disposed along mutually opposed two sides (or four sides) of the semiconductor chip. However, for example, in a case where a memory cell array and a peripheral circuit thereof are formed on a semiconductor chip, the length of signal wiring lines for connecting a pad array, which is disposed adjacent to the memory cell array, and the peripheral circuit increases. As a result, a problem arises that the wiring resistance and wiring capacitance increase and a signal delay occurs.
Buffer circuits, such as input buffers and output buffers, are provided adjacent to the respective pad arrays. Power supply lines for supplying power to the buffer circuits are needed, leading to an increase in pattern occupation area. In particular, with recent increases in integration density and enhancement in function of semiconductor devices, there is a tendency that the area of an external connection region (pad arrays, power supply lines and buffer circuits), which occupies the surface of the semiconductor chip, increases.
In order to cope with an increase in number of pads, Patent Document 1, for instance, discloses an example of a pad layout and a lead layout, which is adaptive to reduction in size of the semiconductor chip and an increase in number of pins and a decrease in pitch of a package. However, no consideration is given to the length of signal wiring lines and the layout of power supply lines and buffer circuits. The prior art is not satisfactory from the standpoint of suppression of signal delay and reduction in pattern occupation area of the external connection region.
Patent Document 1: Jpn. Pat. Appln. KOKAI Publication No. 9-237800